LU-Decomposition on a Massively Parallel Transputer System

Two algorithms for LU{decomposition on a transputer based reconngurable MIMD parallel computer with distributed memory have been analyzed in view of the interdependence of granularity and execution time. In order to investigate this experimentally, LU{decomposition algorithms have been implemented on a parallel computer, the Parsytec SuperCluster 128. The results of this investigation may be summarized as follows. The LU{decomposition algorithms are very eecient on the parallel computer, if the ratio between problem size and number of processors is not too small. No loss of eeciency is to be expected, if the number of processors is increased only proportionally to the number of elements in the matrix being decomposed. The parallel computer Parsytec SuperCluster 128 (SC 128) is a massively parallel transputer system with distributed memory and 128 processors of type T805 plus some special purpose processors 10]. In the SC 128 the transputers are connected by a statically reconngurable interprocessor network built from 12 Network Connguration Units (NCUs) 10, 11]. Each NCU is a 9696 crossbar switch for link connections. Software running on the SC 128 must be based on message passing. Examplary parallel LU-decomposition algorithms have been implemented on this parallel computer to investigate parallel algorithms 7]. These algorithms decompose a matrix M into a lower triangular matrix L and an upper triangular matrix U with M = L U. One of the matrices L and U is unit upper/lower triangular. The parallel algorithms are derived from the algorithms of Crout and of Doolittle, which diier in the choice of the unit All algorithms described in this paper require a processor network with a torus structure of p p processors. An ideal torus structure occupies all four links of each transputer and allows no entry into the processor network. Therefore, an additional transputer must be inserted into one of the link connections. A free link of this transputer provides the entry into the processor network. During